A display image is generally is processed by a graphics controller of a host device composed of a personal computer (PC) and the like, and then transferred to a display device. However, owing to the recent advance of the display devices as typified by a liquid crystal display (LCD) panel, a large difference in a processing capability between the host device and the display device has emerged. For example, in the LCD panel, a high resolution of the panel itself is developed, and an ultra-high-resolution panels showing a resolution of a very high resolution, such as Quad Extended Graphics Array (QXGA, 2048.times.1536 dots), Quad Super Extended Graphics Array (QSXGA, 2560.times.2048 dots) and Quad Ultra Extended Graphics Array (QUXGA, 3200.times.2400 dots), have been put into practical use. On the contrary, system power and power of the graphics controller come to be incapable of following the advance of the panel, and a satisfactory display on the ultra-high-resolution panel is practically impossible.
Performance of an image processing system as typified by the graphics controller is limited to the QXGA level in terms of general display functions, and in a three-dimensional (3D) computer graphics (CG), as typified by home video game machines, the performance of the image processing system only can exhibit a processing capability of a resolution as low as Video Graphics Array (VGA, 640.times.480 dots). As described above, while the most advanced moving picture shows still a resolution of about the VGA level, the panels exhibiting a resolution several times to several ten times as high as the VGA comes to be manufactured, and a remarkable difference in the processing capability appears.
On the other hand, the display device as typified by the LCD panel has recently a further smaller picture frame that is a periphery of its display portion, and a so-called tiling in which a magnified panel is made by gathering a plurality of panels together comes to be possible. As a result, it is possible to further increase a resolution on the panel side, and hence a gap between the panel side and the host side appears more remarkably.
As first means for solving a deficiency of power in the graphics chip, a system constitution, for example, shown in FIG. 18 is conceived. In this system constitution, a high-resolution panel 201 on the panel side 200 is divided into four regions, and a plurality of panel control chips 202 of the number corresponding to that of the four regions are provided. Reference numeral 203 denotes a display dividing line for dividing the panel 201. On the other hand, on the host side 210, graphics chips 211 of the same number as that of the panel control chips 202 are provided, and connected to the corresponding control chips 202, respectively, via the digital interface (I/F) lines 220 of the same number as the graphics chips 211. In the graphics chips 211, the graphics memory 212 are respectively provided. Display data from an application is multi-inputted to the respective graphics chips 211 via the system bus 213. According to this technology, even though a processing capability of each graphics chip 211 is low, the display data can be processed, for example, by four graphics chips 211, and hence the problem of the processing capability can be solved.
As second means for solving a deficiency of power in the graphics chip, a method in which a memory is provided on a display device side, and a transfer speed is lowered to a technically feasible transfer rate is conceived. To be more specific, only one graphics chip is provided on the host side, and is connected to a graphics memory in which a capacity for all panels is secured. On the other hand, a panel memory is provided for the panel control chip on the monitor side. After the image data is developed in the graphics memory on the host side, the transfer speed is lowered in accordance with a shortfall of the processing capability, and then the image data is transmitted to the monitor side. The image data transmitted to the monitor side is once stored in the panel memory by means of the panel control chip, and then refreshing of the screen is performed. According to the second means, the intact refreshing rate can be adopted by lowering the transfer speed, and a high-resolution still picture can be displayed.
By adopting the foregoing means, even when a graphics chip showing a low processing capability is used, it is possible to display an image on a high-resolution panel prima facie.
However, the foregoing first means poses a first problem that an image processing of divided screens is greatly constrained, the divided screens striding the display dividing line 203 of the panel 201 shown in FIG. 18. For example, when original image data is not QXGA, the divided image data must be transmitted to the graphics chip 211 from the beginning in a state where VGA and Extended Graphics Array (XGA, 1024.times.768 dots) are magnified. Specifically, it is required that they are magnified beyond the boundary, and the image data is outputted to the magnified screen. This implies that the host side 210 splits the image data every time the resolution of the display screen changes depending on the system, and transfers the split image data to the graphics chip 211. Most of the current applications are scheduled only for an operation to write the image data onto one screen, it is substantially impossible to execute an operation to split the screen and division ally develop the image data for each chip by the current application.
As a second problem involved in the foregoing first means, because of the multi-inputs from the common system bus 213 to the respective graphics chips 211, the performance of the system bus 213 becomes a bottleneck of the processing for the whole of the system. As this system bus 213, there are two types that are a peripheral component interconnect (PCI) bus and an accelerated graphics port (AGP). The AGP has a performance eight times or higher than that of the PCI bus. In the large quantity of image data transfer, which is performed for the 3D graphics, for example, the PCI bus shows a lack of capability, and it is necessary to use the AGP exhibiting a high transfer speed. However, the AGP has no bus structure because of its high speed processing, and cannot be multi-connected to the graphics chips, so that the AGP adopts the one-to-one data processing. For this reason, in the case where the plurality of graphics chips 211 exist as shown in FIG. 18, the AGP cannot be employed, so that the performance of the system bus 213 cannot be improved.
On the other hand, the foregoing second means can solve the foregoing two problems of the system bus and the scaling of the screen discontinuity in the first means. However, although the second means can display the image data if the transfer speed is lowered to one-quarter, the reduction in the transfer speed poses a new problem. Specifically, when a moving picture is displayed, frames are missed due to the slow transfer speed. It is impossible to perform writing with the expected speed, for example, of 60 Hz. The second means cannot realize the window display in which still and moving pictures with high resolution mixedly exist.